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Proceedings Paper

RPython high-level synthesis
Author(s): Radoslaw Cieszewski; Maciej Linczuk
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Paper Abstract

The development of FPGA technology and the increasing complexity of applications in recent decades have forced compilers to move to higher abstraction levels. Compilers interprets an algorithmic description of a desired behavior written in High-Level Languages (HLLs) and translate it to Hardware Description Languages (HDLs). This paper presents a RPython based High-Level synthesis (HLS) compiler. The compiler get the configuration parameters and map RPython program to VHDL. Then, VHDL code can be used to program FPGA chips. In comparison of other technologies usage, FPGAs have the potential to achieve far greater performance than software as a result of omitting the fetch-decode-execute operations of General Purpose Processors (GPUs), and introduce more parallel computation. This can be exploited by utilizing many resources at the same time. Creating parallel algorithms computed with FPGAs in pure HDL is difficult and time consuming. Implementation time can be greatly reduced with High-Level Synthesis compiler. This article describes design methodologies and tools, implementation and first results of created VHDL backend for RPython compiler.

Paper Details

Date Published: 28 September 2016
PDF: 6 pages
Proc. SPIE 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 100314O (28 September 2016); doi: 10.1117/12.2249143
Show Author Affiliations
Radoslaw Cieszewski, Warsaw Univ. of Technology (Poland)
Maciej Linczuk, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 10031:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016
Ryszard S. Romaniuk, Editor(s)

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