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Proceedings Paper

Automatic latency equalization in VHDL-implemented complex pipelined systems
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Paper Abstract

In the pipelined data processing systems it is very important to ensure that parallel paths delay data by the same number of clock cycles. If that condition is not met, the processing blocks receive data not properly aligned in time and produce incorrect results. Manual equalization of latencies is a tedious and error-prone work. This paper presents an automatic method of latency equalization in systems described in VHDL. The proposed method uses simulation to measure latencies and verify introduced correction. The solution is portable between different simulation and synthesis tools. The method does not increase the complexity of the synthesized design comparing to the solution based on manual latency adjustment. The example implementation of the proposed methodology together with a simple design demonstrating its use is available as an open source project under BSD license.

Paper Details

Date Published: 28 September 2016
PDF: 12 pages
Proc. SPIE 10031, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016, 1003145 (28 September 2016); doi: 10.1117/12.2247943
Show Author Affiliations
Wojciech M. Zabołotny, Warsaw Univ. of Technology (Poland)
Univ. of Warsaw (Poland)


Published in SPIE Proceedings Vol. 10031:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2016
Ryszard S. Romaniuk, Editor(s)

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