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Proceedings Paper

Optimization of J-V characteristic in diode array for phase change memory
Author(s): Heng Wang; Yan Liu; Bo Liu; Chao Zhang; Zhitang Song
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Paper Abstract

In this paper, current density-voltage (J-V) characteristic of dual trench diode array have been investigated by both TCAD model and experimental method. It is shown that the arsenic concentration in buried N+ layer (BNL), epitaxial (EPI) layer thickness, and the dosage of P region in PN junction are expected to be the prominent factors responsible for both of the leakage and drive current performance according to TCAD simulation. By introducing the optimal siliconbased results, the 4×4 diode arrays were successfully manufactured by 40nm CMOS technology. The median values of drive and reverse leakage current densities are ~7.30×10-2 A/μm2 and 5.61×10-9 A/μm2, respectively. The breakdown voltages (BVDs) of diode array are exceeding 6V, and the Jon/Joff ratios of ~109, which can satisfy the requirements of phase change memory (PCM) applications.

Paper Details

Date Published: 12 October 2016
PDF: 6 pages
Proc. SPIE 9818, 2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage, 98180R (12 October 2016); doi: 10.1117/12.2246915
Show Author Affiliations
Heng Wang, Shanghai Institute of Microsystem and Information Technology (China)
Yan Liu, Shanghai Institute of Microsystem and Information Technology (China)
Bo Liu, Shanghai Institute of Microsystem and Information Technology (China)
Chao Zhang, Semiconductor Manufacturing International Corp. (China)
Zhitang Song, Shanghai Institute of Microsystem and Information Technology (China)


Published in SPIE Proceedings Vol. 9818:
2016 International Workshop on Information Data Storage and Tenth International Symposium on Optical Storage
Fuxi Gan; Zhitang Song; Yang Wang, Editor(s)

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