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Proceedings Paper

Implementation of an FPGA-based DCDS video processor for CCD imaging
Author(s): Simon Tulloch
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Paper Abstract

Noise modeling of an E2V CCD231 suggested that a weighted double correlated sampler (DCDS) processor could offer small noise improvements at low pixel rates. The model was used to produce synthetic video waveforms that were then processed at various ADC frequencies and analogue bandwidths to identify the best weighting strategy and preamplifier design. An FPGA-based DCDS controller was then built, first to measure the actual CCD noise spectrum and then to verify the earlier theoretical results.

Paper Details

Date Published: 27 July 2016
PDF: 17 pages
Proc. SPIE 9915, High Energy, Optical, and Infrared Detectors for Astronomy VII, 991530 (27 July 2016); doi: 10.1117/12.2240405
Show Author Affiliations
Simon Tulloch, European Southern Observatory (Germany)


Published in SPIE Proceedings Vol. 9915:
High Energy, Optical, and Infrared Detectors for Astronomy VII
Andrew D. Holland; James Beletic, Editor(s)

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