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A physical resist shrinkage model for full-chip lithography simulations
Author(s): Peng Liu; Leiwu Zheng; Maggie Ma; Qian Zhao; Yongfa Fan; Qiang Zhang; Mu Feng; Xin Guo; Tom Wallow; Keith Gronlund; Ronald Goossens; Gary Zhang; Yenwen Lu
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Paper Abstract

Strong resist shrinkage effects have been widely observed in resist profiles after negative tone development (NTD) and therefore must be taken into account in computational lithography applications. However, existing lithography simulation tools, especially those designed for full-chip applications, lack resist shrinkage modeling capabilities because they are not needed until only recently when NTD processes begin to replace the conventional positive tone development (PTD) processes where resist shrinkage effects are negligible. In this work we describe the development of a physical resist shrinkage (PRS) model for full-chip lithography simulations and present its accuracy evaluation against experimental data.

Paper Details

Date Published: 25 March 2016
PDF: 10 pages
Proc. SPIE 9779, Advances in Patterning Materials and Processes XXXIII, 97790Y (25 March 2016); doi: 10.1117/12.2239243
Show Author Affiliations
Peng Liu, ASML Brion (United States)
Leiwu Zheng, ASML Brion (United States)
Maggie Ma, ASML Brion (United States)
Qian Zhao, ASML Brion (United States)
Yongfa Fan, ASML Brion (United States)
Qiang Zhang, ASML Brion (United States)
Mu Feng, ASML Brion (United States)
Xin Guo, ASML Brion (United States)
Tom Wallow, ASML Brion (United States)
Keith Gronlund, ASML Brion (United States)
Ronald Goossens, ASML Brion (United States)
Gary Zhang, ASML Brion (United States)
Yenwen Lu, ASML Brion (United States)


Published in SPIE Proceedings Vol. 9779:
Advances in Patterning Materials and Processes XXXIII
Christoph K. Hohle; Rick Uchida, Editor(s)

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