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Proceedings Paper

Fabrication of cross-shaped Cu-nanowire resistive memory devices using a rapid, scalable, and designable inorganic-nanowire-digital-alignment technique (Conference Presentation)
Author(s): Wentao Xu; Yeongjun Lee; Sung-Yong Min; Cheolmin Park; Tae-Woo Lee
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Paper Abstract

Resistive random-access memory (RRAM) is a candidate next generation nonvolatile memory due to its high access speed, high density and ease of fabrication. Especially, cross-point-access allows cross-bar arrays that lead to high-density cells in a two-dimensional planar structure. Use of such designs could be compatible with the aggressive scaling down of memory devices, but existing methods such as optical or e-beam lithographic approaches are too complicated. One-dimensional inorganic nanowires (i-NWs) are regarded as ideal components of nanoelectronics to circumvent the limitations of conventional lithographic approaches. However, post-growth alignment of these i-NWs precisely on a large area with individual control is still a difficult challenge. Here, we report a simple, inexpensive, and rapid method to fabricate two-dimensional arrays of perpendicularly-aligned, individually-conductive Cu-NWs with a nanometer-scale CuxO layer sandwiched at each cross point, by using an inorganic-nanowire-digital-alignment technique (INDAT) and a one-step reduction process. In this approach, the oxide layer is self-formed and patterned, so conventional deposition and lithography are not necessary. INDAT eliminates the difficulties of alignment and scalable fabrication that are encountered when using currently-available techniques that use inorganic nanowires. This simple process facilitates fabrication of cross-point nonvolatile memristor arrays. Fabricated arrays had reproducible resistive switching behavior, high on/off current ratio (Ion/Ioff) ~10 6 and extensive cycling endurance. This is the first report of memristors with the resistive switching oxide layer self-formed, self-patterned and self-positioned; we envision that the new features of the technique will provide great opportunities for future nano-electronic circuits.

Paper Details

Date Published: 7 November 2016
PDF: 1 pages
Proc. SPIE 9945, Printed Memory and Circuits II, 99450B (7 November 2016); doi: 10.1117/12.2238683
Show Author Affiliations
Wentao Xu, Pohang Univ. of Science and Technology (Korea, Republic of)
Yeongjun Lee, Pohang Univ. of Science and Technology (Korea, Republic of)
Sung-Yong Min, Pohang Univ. of Science and Technology (Korea, Republic of)
Cheolmin Park, Yonsei Univ. (Korea, Republic of)
Tae-Woo Lee, Pohang Univ. of Science and Technology (Korea, Republic of)


Published in SPIE Proceedings Vol. 9945:
Printed Memory and Circuits II
Emil J. W. List-Kratochvil, Editor(s)

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