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Proceedings Paper

Low-loss CMOS copper plasmonic waveguides at the nanoscale (Conference Presentation)
Author(s): Dmitry Y. Fedyanin; Dmitry I. Yakubovsky; Roman V. Kirtaev; Valentyn S. Volkov
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Paper Abstract

Implementation of optical components in microprocessors can increase their performance by orders of magnitude. However, the size of optical elements is fundamentally limited by diffraction, while miniaturization is one of the essential concepts in the development of high-speed and energy-efficient electronic chips. Surface plasmon polaritons (SPPs) are widely considered to be promising candidates for the next generation of chip-scale technology thanks to the ability to break down the fundamental diffraction limit and manipulate optical signals at the truly nometer scale. In the past years, a variety of deep-subwavelength plasmonic structures have been proposed and investigated, including dielectric-loaded SPP waveguides, V-groove waveguides, hybrid plasmonic waveguides and metal nanowires. At the same time, for practical application, such waveguide structures must be integrated on a silicon chip and be fabricated using CMOS fabrication process. However, to date, acceptable characteristics have been demonstrated only with noble metals (gold and silver), which are not compatible with industry-standard manufacturing technologies. On the other hand, alternative materials introduce enormous propagation losses due absorption in the metal. This prevents plasmonic components from implementation in on-chip nanophotonic circuits. In this work, we experimentally demonstrate for the first time that copper plasmonic waveguides fabricated in a CMOS compatible process can outperform gold waveguides showing the same level of mode confinement and lower propagation losses. At telecommunication wavelengths, the fabricated ultralow-loss deep-subwavelength hybrid plasmonic waveguides ensure a relatively long propagation length of more than 50 um along with strong mode confinement with the mode size down to lambda^2/70, which is confirmed by direct scanning near-field optical microscopy (SNOM) measurements. These results create the backbone for design and development of high-density nanophotonic circuits and their integration with electronic logic on a silicon chip.

Paper Details

Date Published: 27 July 2016
PDF: 1 pages
Proc. SPIE 9891, Silicon Photonics and Photonic Integrated Circuits V, 989109 (27 July 2016); doi: 10.1117/12.2227929
Show Author Affiliations
Dmitry Y. Fedyanin, Moscow Institute of Physics and Technology (Russian Federation)
Dmitry I. Yakubovsky, Moscow Institute of Physics and Technology (Russian Federation)
Roman V. Kirtaev, Moscow Institute of Physics and Technology (Russian Federation)
Valentyn S. Volkov, Moscow Institute of Physics and Technology (Russian Federation)
Univ. of Southern Denmark (Denmark)

Published in SPIE Proceedings Vol. 9891:
Silicon Photonics and Photonic Integrated Circuits V
Laurent Vivien; Lorenzo Pavesi; Stefano Pelli, Editor(s)

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