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Proceedings Paper

Hybrid overlay metrology for high order correction by using CDSEM
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Paper Abstract

Overlay control has become one of the most critical issues for semiconductor manufacturing. Advanced lithographic scanners use high-order corrections or correction per exposure to reduce the residual overlay. It is not enough in traditional feedback of overlay measurement by using ADI wafer because overlay error depends on other process (etching process and film stress, etc.). It needs high accuracy overlay measurement by using AEI wafer. WIS (Wafer Induced Shift) is the main issue for optical overlay, IBO (Image Based Overlay) and DBO (Diffraction Based Overlay). We design dedicated SEM overlay targets for dual damascene process of N10 by i-ArF multi-patterning. The pattern is same as device-pattern locally. Optical overlay tools select segmented pattern to reduce the WIS. However segmentation has limit, especially the via-pattern, for keeping the sensitivity and accuracy. We evaluate difference between the viapattern and relaxed pitch gratings which are similar to optical overlay target at AEI. CDSEM can estimate asymmetry property of target from image of pattern edge. CDSEM can estimate asymmetry property of target from image of pattern edge. We will compare full map of SEM overlay to full map of optical overlay for high order correction ( correctables and residual fingerprints).

Paper Details

Date Published: 8 April 2016
PDF: 8 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 977824 (8 April 2016); doi: 10.1117/12.2222777
Show Author Affiliations
Philippe Leray, IMEC (Belgium)
Sandip Halder, IMEC (Belgium)
Gian Lorusso, IMEC (Belgium)
Bart Baudemprez, IMEC (Belgium)
Osamu Inoue, Hitachi High Technology (Japan)
Yutaka Okagawa, Hitachi High Technology (Japan)


Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)

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