Share Email Print
cover

Proceedings Paper

Design strategy for integrating DSA via patterning in sub-7 nm interconnects
Author(s): Ioannis Karageorgos; Julien Ryckaert; Maryann C. Tung; H.-S. Philip Wong; Roel Gronheid; Joost Bekaert; Evangelos Karageorgos; Kris Croes; Geert Vandenberghe; Michele Stucchi; Wim Dehaene
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In recent years, major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCPs). As a result, the insertion of DSA for IC fabrication is being actively considered for the sub-7nm nodes. At these nodes the DSA technology could alleviate costs for multiple patterning and limit the number of litho masks that would be required per metal layer. One of the most straightforward approaches for DSA implementation would be for via patterning through templated DSA, where hole patterns are readily accessible through templated confinement of cylindrical phase BCP materials.

Our in-house studies show that decomposition of via layers in realistic circuits below the 7nm node would require at least many multi-patterning steps (or colors), using 193nm immersion lithography. Even the use of EUV might require double patterning in these dimensions, since the minimum via distance would be smaller than EUV resolution. The grouping of vias through templated DSA can resolve local conflicts in high density areas. This way, the number of required colors can be significantly reduced.

For the implementation of this approach, a DSA-aware mask decomposition is required. In this paper, our design approach for DSA via patterning in sub-7nm nodes is discussed. We propose options to expand the list of DSA-compatible via patterns (DSA letters) and we define matching cost formulas for the optimal DSA-aware layout decomposition. The flowchart of our proposed approach tool is presented.

Paper Details

Date Published: 16 March 2016
PDF: 9 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810N (16 March 2016); doi: 10.1117/12.2222041
Show Author Affiliations
Ioannis Karageorgos, IMEC (Belgium)
KU Leuven (Belgium)
Julien Ryckaert, IMEC (Belgium)
Maryann C. Tung, Stanford Univ. (United States)
H.-S. Philip Wong, Stanford Univ. (United States)
Roel Gronheid, IMEC (Belgium)
Joost Bekaert, IMEC (Belgium)
Evangelos Karageorgos, National and Kapodistrian Univ. of Athens (Greece)
Kris Croes, IMEC (Belgium)
Geert Vandenberghe, IMEC (Belgium)
Michele Stucchi, IMEC (Belgium)
Wim Dehaene, KU Leuven (Belgium)
IMEC (Belgium)


Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

© SPIE. Terms of Use
Back to Top