Share Email Print
cover

Proceedings Paper

Intra-lot wafer by wafer overlay control using integrated and standalone metrology combined sampling
Author(s): Young Sin Choi; Young Sun Nam; Dong Han Lee; Jae Il Lee; Young Seog Kang; Se Yeon Jang; Jeong Heung Kong
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry’s preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement.

In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.

Paper Details

Date Published: 15 March 2016
PDF: 6 pages
Proc. SPIE 9780, Optical Microlithography XXIX, 978009 (15 March 2016); doi: 10.1117/12.2219922
Show Author Affiliations
Young Sin Choi, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Young Sun Nam, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Dong Han Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jae Il Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Young Seog Kang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Se Yeon Jang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jeong Heung Kong, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)


Published in SPIE Proceedings Vol. 9780:
Optical Microlithography XXIX
Andreas Erdmann; Jongwook Kye, Editor(s)

© SPIE. Terms of Use
Back to Top