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Proceedings Paper

Variability-aware compact modeling and statistical circuit validation on SRAM test array
Author(s): Ying Qiao; Costas J. Spanos
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Paper Abstract

Variability modeling at the compact transistor model level can enable statistically optimized designs in view of limitations imposed by the fabrication technology. In this work we propose a variability-aware compact model characterization methodology based on stepwise parameter selection. Transistor I-V measurements are obtained from bit transistor accessible SRAM test array fabricated using a collaborating foundry’s 28nm FDSOI technology. Our in-house customized Monte Carlo simulation bench can incorporate these statistical compact models; and simulation results on SRAM writability performance are very close to measurements in distribution estimation. Our proposed statistical compact model parameter extraction methodology also has the potential of predicting non-Gaussian behavior in statistical circuit performances through mixtures of Gaussian distributions.

Paper Details

Date Published: 16 March 2016
PDF: 9 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810D (16 March 2016); doi: 10.1117/12.2219428
Show Author Affiliations
Ying Qiao, Univ. of California, Berkeley (United States)
Costas J. Spanos, Univ. of California, Berkeley (United States)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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