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Proceedings Paper

Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs
Author(s): Hongyi Liu; Chuyang Hong; Ting Han; Jun Zhou; Yijian Chen
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Paper Abstract

As optical lithography and conventional transistor structure are approaching their physical limits, 3D vertical gate-all-around (GAA) nanowire MOSFETs and double-surrounding-gate (DSG) MOSFETs are two promising device candidates for post-FinFET logic scaling owing to their superior gate control and scaling potential. However, source, drain and gate of a vertical nanowire MOSFET and DSG MOSFETs are located in different physical layers. Consequently, structural design of IC devices/circuits, layout arrangement for high-density vertical nanowires/interconnects, and routing strategy are non-trivial challenges. In this paper, we shall discuss these critical issues for constructing standard cells using 3D vertical GAA nanowire MOSFETs and DSG MOSFETs. We redesigned the standard cells in Nangate Open Cell Library for 5nm node using vertical GAA nanowire MOSFETs and DSG MOSFETs. Experimental results verify the functionality of the proposed standard cell layout design approach.

Paper Details

Date Published: 16 March 2016
PDF: 11 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978103 (16 March 2016); doi: 10.1117/12.2219267
Show Author Affiliations
Hongyi Liu, Peking Univ. (China)
Chuyang Hong, Peking Univ (China)
Ting Han, Peking Univ. (China)
Jun Zhou, Peking Univ. (China)
Yijian Chen, Peking Univ. (China)


Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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