Share Email Print

Proceedings Paper

Reducing overlay sampling for APC-based correction per exposure by replacing measured data with computational prediction
Author(s): Ben F. Noyes; Babak Mokaberi; Jong Hun Oh; Hyun Sik Kim; Jun Ha Sung; Marc Kea
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

One of the keys to successful mass production of sub-20nm nodes in the semiconductor industry is the development of an overlay correction strategy that can meet specifications, reduce the number of layers that require dedicated chuck overlay, and minimize measurement time. Three important aspects of this strategy are: correction per exposure (CPE), integrated metrology (IM), and the prioritization of automated correction over manual subrecipes.

The first and third aspects are accomplished through an APC system that uses measurements from production lots to generate CPE corrections that are dynamically applied to future lots. The drawback of this method is that production overlay sampling must be extremely high in order to provide the system with enough data to generate CPE. That drawback makes IM particularly difficult because of the throughput impact that can be created on expensive bottleneck photolithography process tools.

The goal is to realize the cycle time and feedback benefits of IM coupled with the enhanced overlay correction capability of automated CPE without impacting process tool throughput. This paper will discuss the development of a system that sends measured data with reduced sampling via an optimized layout to the exposure tool’s computational modelling platform to predict and create “upsampled” overlay data in a customizable output layout that is compatible with the fab user CPE APC system. The result is dynamic CPE without the burden of extensive measurement time, which leads to increased utilization of IM.

Paper Details

Date Published: 8 March 2016
PDF: 6 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 977832 (8 March 2016); doi: 10.1117/12.2219241
Show Author Affiliations
Ben F. Noyes, SAMSUNG Austin Semiconductor LLC (United States)
Babak Mokaberi, SAMSUNG Austin Semiconductor LLC (United States)
Jong Hun Oh, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Hyun Sik Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jun Ha Sung, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Marc Kea, ASML Netherlands B.V. (Netherlands)

Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)

© SPIE. Terms of Use
Back to Top