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Proceedings Paper

Expanding the printable design space for lithography processes utilizing a cut mask
Author(s): Jerome Wandell; Mohamed Salama; William Wilkinson; Mark Curtice; Jui-Hsuan Feng; Shao Wen Gao; Abhishek Asthana
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Paper Abstract

The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer.

This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.

Paper Details

Date Published: 23 March 2016
PDF: 12 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978112 (23 March 2016); doi: 10.1117/12.2219201
Show Author Affiliations
Jerome Wandell, GLOBALFOUNDRIES Inc. (United States)
Mohamed Salama, GLOBALFOUNDRIES Inc. (United States)
William Wilkinson, GLOBALFOUNDRIES Inc. (United States)
Mark Curtice, GLOBALFOUNDRIES Inc. (United States)
Jui-Hsuan Feng, GLOBALFOUNDRIES Inc. (United States)
Shao Wen Gao, GLOBALFOUNDRIES Inc. (United States)
Abhishek Asthana, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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