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Proceedings Paper

Design for nanoimprint lithography: total layout refinement utilizing NIL process simulation
Author(s): Sachiko Kobayashi; Motofumi Komori; Inanami Ryoichi; Kyoji Yamashita; Akiko Mimotogi; Ji-Young Im; Masayuki Hatano; Takuya Kono; Shimon Maeda
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Paper Abstract

Technologies for pattern fabrication using Nanoimprint lithography (NIL) process are being developed for various devices. NIL is an attractive and promising candidate for its pattern fidelity toward 1z device fabrication without additional usage of double patterning process. Layout dependent hotspots become a significant issue for application in small pattern size device, and design for manufacturing (DFM) flow for imprint process becomes significantly important. In this paper, simulation of resist spread in fine pattern of various scales are demonstrated and the fluid models depending on the scale are proposed. DFM flow to prepare imprint friendly design, issues for sub-20 nm NIL are proposed.

Paper Details

Date Published: 22 March 2016
PDF: 7 pages
Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 977708 (22 March 2016); doi: 10.1117/12.2219052
Show Author Affiliations
Sachiko Kobayashi, Toshiba Corp. (Japan)
Motofumi Komori, Toshiba Corp. (Japan)
Inanami Ryoichi, Toshiba Corp. (Japan)
Kyoji Yamashita, Toshiba Corp. (Japan)
Akiko Mimotogi, Toshiba Corp. (Japan)
Ji-Young Im, Toshiba Corp. (Japan)
Masayuki Hatano, Toshiba Corp. (Japan)
Takuya Kono, Toshiba Corp. (Japan)
Shimon Maeda, Toshiba Corp. (Japan)

Published in SPIE Proceedings Vol. 9777:
Alternative Lithographic Technologies VIII
Christopher Bencher, Editor(s)

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