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Proceedings Paper

Electron-beam lithography with character projection exposure for throughput enhancement with line-edge quality optimization
Author(s): Rimon Ikeno; Satoshi Maruyama; Yoshio Mita; Makoto Ikeda; Kunihiro Asada
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Paper Abstract

Among various electron-beam lithography (EBL) techniques, variable-shaped beam (VSB) and character projection (CP) methods have attracted many EBL users for their high-throughput feature, but they are considered to be more suited to small-featured VLSI fabrication with regularly-arranged layouts like standard-cell logics and memory arrays. On the other hand, non-VLSI applications like photonics, MEMS, MOEMS, and so on, have not been fully utilized the benefit of CP method due to their wide variety of layout patterns. In addition, the stepwise edge shapes by VSB method often causes intolerable edge roughness to degrade device characteristics from its intended performance with smooth edges.

We proposed an overall EBL methodology applicable to wade-variety of EBL applications utilizing VSB and CP methods. Its key idea is in our layout data conversion algorithm that decomposes curved or oblique edges of arbitrary layout patterns into CP shots. We expect significant reduction in EB shot count with a CP-bordered exposure data compared to the corresponding VSB-alone conversion result. Several CP conversion parameters are used to optimize EB exposure throughput, edge quality, and resultant device characteristics.

We demonstrated out methodology using the leading-edge VSB/CP EBL tool, ADVANTEST F7000S-VD02, with high resolution Hydrogen Silsesquioxane (HSQ) resist. Through our experiments of curved and oblique edge lithography under various data conversion conditions, we learned correspondence of the conversion parameters to the resultant edge roughness and other conditions. They will be utilized as the fundamental data for further enhancement of our EBL strategy for optimized EB exposure.

Paper Details

Date Published: 16 March 2016
PDF: 9 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978110 (16 March 2016); doi: 10.1117/12.2219021
Show Author Affiliations
Rimon Ikeno, The Univ. of Tokyo (Japan)
Satoshi Maruyama, The Univ. of Tokyo (Japan)
Yoshio Mita, The Univ. of Tokyo (Japan)
Makoto Ikeda, The Univ. of Tokyo (Japan)
Kunihiro Asada, The Univ. of Tokyo (Japan)


Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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