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Proceedings Paper

Using pattern analysis methods to do fast detection of manufacturing pattern failures
Author(s): Evan Zhao; Jessie Wang; Mason Sun; Jeff Wang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai; Hua Ding
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Paper Abstract

At the advanced technology node, logic design has become extremely complex and is getting more challenging as the pattern geometry size decreases. The small sizes of layout patterns are becoming very sensitive to process variations. Meanwhile, the high pressure of yield ramp is always there due to time-to-market competition. The company that achieves patterning maturity earlier than others will have a great advantage and a better chance to realize maximum profit margins.

For debugging silicon failures, DFT diagnostics can identify which nets or cells caused the yield loss. But normally, a long time period is needed with many resources to identify which failures are due to one common layout pattern or structure. This paper will present a new yield diagnostic flow, based on preliminary EFA results, to show how pattern analysis can more efficiently detect pattern related systematic defects. Increased visibility on design pattern related failures also allows more precise yield loss estimation.

Paper Details

Date Published: 16 March 2016
PDF: 7 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810Z (16 March 2016); doi: 10.1117/12.2219000
Show Author Affiliations
Evan Zhao, Semiconductor Manufacturing International Corp. (China)
Jessie Wang, Semiconductor Manufacturing International Corp. (China)
Mason Sun, Semiconductor Manufacturing International Corp. (China)
Jeff Wang, Semiconductor Manufacturing International Corp. (China)
Yifan Zhang, Cadence Design Systems, Inc. (United States)
Jason Sweis, Cadence Design Systems, Inc. (United States)
Ya-Chieh Lai, Cadence Design Systems, Inc. (United States)
Hua Ding, Cadence Design Systems, Inc. (United States)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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