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Proceedings Paper

Impacts of process variability of alternating-material self-aligned multiple patterning on SRAM circuit performance
Author(s): Ting Han; Chuyang Hong; Qi Cheng; Yijian Chen
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Paper Abstract

In this paper, we propose a novel modular patterning technology to reduce the edge-placement errors (EPE) significantly by combining alternating-material self-aligned multiple patterning (altSAMP) and selective etching processes. It is assumed that gates and fins are fabricated by the same type of altSAMP process as mixing two different processing techniques will drive up the manufacturing costs. Process variability induced circuit performance degradation is shown to be a serious issue as FinFET devices are scaled down to sub-10nm. We analyze the dependence of FinFET-based SRAM circuit performance on supply voltage, fin-width and gate-length variations. Improved device control with narrower fins helps to increase the static noise margin (SNM) in all SRAM cell designs. Higher supply voltage is also beneficial to the SNM performance. Our simulation results show that 6-T SRAM circuit design does not meet the six-sigma yield requirement when the half pitch is scaled down to sub-7 nm. To reduce the SRAM circuit variability, we study an 8-T SRAM cell and show that it significantly improves the SRAM performance.

Paper Details

Date Published: 16 March 2016
PDF: 10 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810E (16 March 2016); doi: 10.1117/12.2218992
Show Author Affiliations
Ting Han, Peking Univ. (China)
Chuyang Hong, Peking Univ. (China)
Qi Cheng, Peking Univ. (China)
Yijian Chen, Peking Univ. (China)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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