Share Email Print

Proceedings Paper

Contact/Via placement management for N7 logic and beyond
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout. [1] In particular Fin, Gate and Metal layers are based on grating with cutting/blocking scheme, these process have become high volume manufacturing techniques in N14 and beyond.[2,3] On the other hand, immersions based pitch scaling of contact hole, via and cutmask processes are required multiple lithography and etching passes.[4] Overlay management is not only the overlay accuracy of layer to layer, to determine the placement error and patterning fidelity in single layer. In this work, focusing on the placement in hole pattern, total placement error budget will be discussed from the viewpoints of metrology, inspection, Mask, OPC and wafer processing. In addition, hole shrink and hole healing techniques have more significant factors in terms of design-process technology co-optimization for N7 and beyond.[5]

Paper Details

Date Published: 25 March 2016
PDF: 9 pages
Proc. SPIE 9779, Advances in Patterning Materials and Processes XXXIII, 97790M (25 March 2016); doi: 10.1117/12.2218976
Show Author Affiliations
Kenichi Oyama, Tokyo Electron Ltd. (Japan)
Arisa Hara, Tokyo Electron Ltd. (Japan)
Kyohei Koike, Tokyo Electron Ltd. (Japan)
Masatoshi Yamato, Tokyo Electron Ltd. (Japan)
Shohei Yamauchi, Tokyo Electron Ltd. (Japan)
Sakurako Natori, Tokyo Electron Ltd. (Japan)
Hidetami Yaegashi, Tokyo Electron Ltd. (Japan)

Published in SPIE Proceedings Vol. 9779:
Advances in Patterning Materials and Processes XXXIII
Christoph K. Hohle; Rick Uchida, Editor(s)

© SPIE. Terms of Use
Back to Top