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Proceedings Paper

Enablement of DSA for VIA layer with a metal SIT process flow
Author(s): L. Schneider; V. Farys; E. Serret; C. Fenouillet-Beranger
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Paper Abstract

For technologies beyond 10 nm, 1D gridded designs are commonly used. This practice is common particularly in the case of Self-Aligned Double Patterning (SADP) metal processes where Vertical Interconnect Access (VIA) connecting metal line layers are placed along a discrete grid thus limiting the number of VIA pitches. In order to create a Vertical Interconnect Access (VIA) layer, graphoepitaxy Directed Self-Assembly (DSA) is the prevailing candidate. The technique relies on the creation of a confinement guide using optical microlithography methods, in which the BCP is allowed to separate into distinct regions. The resulting patterns are etched to obtain an ordered VIA layer.

Guiding pattern variations impact directly on the placement of the target and one must ensure that it does not interfere with circuit performance. To prevent flaws, design rules are set. In this study, for the first time, an original framework is presented to find a consistent set of design rules for enabling the use of DSA in a production flow using Self Aligned Double Patterning (SADP) for metal line layer printing.

In order to meet electrical requirements, the intersecting area between VIA and metal lines must be sufficient to ensure correct electrical connection. The intersecting area is driven by both VIA placement variability and metal line printing variability. Based on multiple process assumptions for a 10 nm node, the Monte Carlo method is used to set a maximum threshold for VIA placement error.

In addition, to determine a consistent set of design rules, representative test structures have been created and tested with our in-house placement estimator: the topological skeleton of the guiding pattern [1]. Using this technique, structures with deviation above the maximum tolerated threshold are considered as infeasible and the appropriate set of design rules is extracted. In a final step, the design rules are verified with further test structures that are randomly generated using percolation in order to emulate a Placed and Routed (P&R) standard cell block.

Paper Details

Date Published: 16 March 2016
PDF: 11 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810O (16 March 2016); doi: 10.1117/12.2218808
Show Author Affiliations
L. Schneider, STMicroelectronics (France)
CEA-LETI (France)
V. Farys, STMicroelectronics (France)
E. Serret, STMicroelectronics (France)
C. Fenouillet-Beranger, CEA-LETI (France)


Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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