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Proceedings Paper

A random approach of test macro generation for early detection of hotspots
Author(s): Jong-hyun Lee; Chin Kim; Minsoo Kang; Sungwook Hwang; Jae-seok Yang; Mohammed Harb; Mohamed Al-Imam; Kareem Madkour; Wael ElManhawy; Joe Kwan
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Paper Abstract

Multiple-Patterning Technology (MPT) is still the preferred choice over EUV for the advanced technology nodes, starting the 20nm node. Down the way to 7nm and 5nm nodes, Self-Aligned Multiple Patterning (SAMP) appears to be one of the effective multiple patterning techniques in terms of achieving small pitch of printed lines on wafer, yet its yield is in question. Predicting and enhancing the yield in the early stages of technology development are some of the main objectives for creating test macros on test masks. While conventional yield ramp techniques for a new technology node have relied on using designs from previous technology nodes as a starting point to identify patterns for Design of Experiment (DoE) creation, these techniques are challenging to apply in the case of introducing an MPT technique like SAMP that did not exist in previous nodes.

This paper presents a new strategy for generating test structures based on random placement of unit patterns that can construct more meaningful bigger patterns. Specifications governing the relationships between those unit patterns can be adjusted to generate layout clips that look like realistic SAMP designs. A via chain can be constructed to connect the random DoE of SAMP structures through a routing layer to external pads for electrical measurement. These clips are decomposed according to the decomposition rules of the technology into the appropriate mandrel and cut masks. The decomposed clips can be tested through simulations, or electrically on silicon to discover hotspots.

The hotspots can be used in optimizing the fabrication process and models to fix them. They can also be used as learning patterns for DFM deck development. By expanding the size of the randomly generated test structures, more hotspots can be detected. This should provide a faster way to enhance the yield of a new technology node.

Paper Details

Date Published: 16 March 2016
PDF: 6 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 97810J (16 March 2016); doi: 10.1117/12.2218806
Show Author Affiliations
Jong-hyun Lee, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Chin Kim, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Minsoo Kang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Sungwook Hwang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Jae-seok Yang, SAMSUNG Electronics Co., Ltd. (Korea, Republic of)
Mohammed Harb, Mentor Graphics Egypt (Egypt)
Mohamed Al-Imam, Mentor Graphics Egypt (Egypt)
Kareem Madkour, Mentor Graphics Egypt (Egypt)
Wael ElManhawy, Mentor Graphics Corp. (United States)
Joe Kwan, Mentor Graphics Corp. (United States)

Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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