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Proceedings Paper

Sub-10nm lines and spaces patterning using grapho-epitaxial directed self-assembly of lamellar block copolymers
Author(s): Yuriko Seino; Hironobu Sato; Yusuke Kasahara; Shinya Minegishi; Ken Miyagi; Hitoshi Kubota; Hideki Kanai; Katsuyoshi Kodera; Masayuki Shiraishi; Naoko Kihara; Yoshiaki Kawamonzen; Toshikatsu Tobana; Katsutoshi Kobayashi; Hitoshi Yamano; Tsukasa Azuma; Satoshi Nomura
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Paper Abstract

Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.

Paper Details

Date Published: 1 April 2016
PDF: 8 pages
Proc. SPIE 9777, Alternative Lithographic Technologies VIII, 97771T (1 April 2016); doi: 10.1117/12.2218787
Show Author Affiliations
Yuriko Seino, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hironobu Sato, EUVL Infrastructure Development Ctr., Inc. (Japan)
Yusuke Kasahara, EUVL Infrastructure Development Ctr., Inc. (Japan)
Shinya Minegishi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Ken Miyagi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hitoshi Kubota, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hideki Kanai, EUVL Infrastructure Development Ctr., Inc. (Japan)
Katsuyoshi Kodera, EUVL Infrastructure Development Ctr., Inc. (Japan)
Masayuki Shiraishi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Naoko Kihara, EUVL Infrastructure Development Ctr., Inc. (Japan)
Yoshiaki Kawamonzen, EUVL Infrastructure Development Ctr., Inc. (Japan)
Toshikatsu Tobana, EUVL Infrastructure Development Ctr., Inc. (Japan)
Katsutoshi Kobayashi, EUVL Infrastructure Development Ctr., Inc. (Japan)
Hitoshi Yamano, EUVL Infrastructure Development Ctr., Inc. (Japan)
Tsukasa Azuma, EUVL Infrastructure Development Ctr., Inc. (Japan)
Satoshi Nomura, EUVL Infrastructure Development Ctr., Inc. (Japan)


Published in SPIE Proceedings Vol. 9777:
Alternative Lithographic Technologies VIII
Christopher Bencher, Editor(s)

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