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Proceedings Paper

Integrated layout based Monte-Carlo simulation for design arc optimization
Author(s): Dongbing Shao; Larry Clevenger; Lei Zhuang; Lars Liebmann; Robert Wong; James Culp
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Paper Abstract

Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

Paper Details

Date Published: 16 March 2016
PDF: 7 pages
Proc. SPIE 9781, Design-Process-Technology Co-optimization for Manufacturability X, 978106 (16 March 2016); doi: 10.1117/12.2218636
Show Author Affiliations
Dongbing Shao, IBM Microelectronics (United States)
Larry Clevenger, IBM Microelectronics (United States)
Lei Zhuang, GLOBALFOUNDRIES Inc. (United States)
Lars Liebmann, GLOBALFOUNDRIES Inc. (United States)
Robert Wong, IBM Microelectronics (United States)
James Culp, GLOBALFOUNDRIES Inc. (United States)


Published in SPIE Proceedings Vol. 9781:
Design-Process-Technology Co-optimization for Manufacturability X
Luigi Capodieci, Editor(s)

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