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Proceedings Paper

HVM metrology challenges towards the 5nm node
Author(s): Benjamin Bunday
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Paper Abstract

This paper will provide a high level overview of the future for in-line high volume manufacturing (HVM) metrology for the semiconductor industry. First, we will take a broad view of the needs of patterned defect, critical dimensional (CD/3D) and films metrology, and present the extensive list of applications for which metrology solutions are needed. Commonalities and differences among the various applications will be shown. We will then report on the gating technical limits of the most important of these metrology solutions to address the metrology challenges of future nodes, highlighting key metrology technology gaps requiring industry attention and investment.

Paper Details

Date Published: 24 March 2016
PDF: 34 pages
Proc. SPIE 9778, Metrology, Inspection, and Process Control for Microlithography XXX, 97780E (24 March 2016); doi: 10.1117/12.2218375
Show Author Affiliations
Benjamin Bunday, SUNY Poly SEMATECH (United States)


Published in SPIE Proceedings Vol. 9778:
Metrology, Inspection, and Process Control for Microlithography XXX
Martha I. Sanchez, Editor(s)

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