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Proceedings Paper

Adaptive gain, equalization, and wavelength stabilization techniques for silicon photonic microring resonator-based optical receivers
Author(s): Samuel Palermo; Patrick Chiang; Kunzhi Yu; Rui Bai; Cheng Li; Chin-Hui Chen; Marco Fiorentino; Ray Beausoleil; Hao Li; Ayman Shafik; Binhao Wang; Alex Titriku
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Paper Abstract

Interconnect architectures based on high-Q silicon photonic microring resonator devices offer a promising solution to address the dramatic increase in datacenter I/O bandwidth demands due to their ability to realize wavelength-division multiplexing (WDM) in a compact and energy efficient manner. However, challenges exist in realizing efficient receivers for these systems due to varying per-channel link budgets, sensitivity requirements, and ring resonance wavelength shifts. This paper reports on adaptive optical receiver design techniques which address these issues and have been demonstrated in two hybrid-integrated prototypes based on microring drop filters and waveguide photodetectors implemented in a 130nm SOI process and high-speed optical front-ends designed in 65nm CMOS. A 10Gb/s powerscalable architecture employs supply voltage scaling of a three inverter-stage transimpedance amplifier (TIA) that is adapted with an eye-monitor control loop to yield the necessary sensitivity for a given channel. As reduction of TIA input-referred noise is more critical at higher data rates, a 25Gb/s design utilizes a large input-stage feedback resistor TIA cascaded with a continuous-time linear equalizer (CTLE) that compensates for the increased input pole. When tested with a waveguide Ge PD with 0.45A/W responsivity, this topology achieves 25Gb/s operation with -8.2dBm sensitivity at a BER=10-12. In order to address microring drop filters sensitivity to fabrication tolerances and thermal variations, efficient wavelength-stabilization control loops are necessary. A peak-power-based monitoring loop which locks the drop filter to the input wavelength, while achieving compatibility with the high-speed TIA offset-correction feedback loop is implemented with a 0.7nm tuning range at 43μW/GHz efficiency.

Paper Details

Date Published: 7 March 2016
PDF: 6 pages
Proc. SPIE 9775, Next-Generation Optical Networks for Data Centers and Short-Reach Links III, 97750K (7 March 2016); doi: 10.1117/12.2214888
Show Author Affiliations
Samuel Palermo, Texas A&M Univ. (United States)
Patrick Chiang, Oregon State Univ. (United States)
Fudan Univ. (China)
Kunzhi Yu, Texas A&M Univ. (United States)
Rui Bai, Hewlett-Packard Co. (United States)
Cheng Li, Hewlett-Packard Co. (United States)
Chin-Hui Chen, Hewlett-Packard Co. (United States)
Marco Fiorentino, Hewlett-Packard Co. (United States)
Ray Beausoleil, Hewlett-Packard Co. (United States)
Hao Li, Oregon State Univ. (United States)
Ayman Shafik, Texas A&M Univ. (United States)
Binhao Wang, Texas A&M Univ. (United States)
Alex Titriku, Texas A&M Univ. (United States)

Published in SPIE Proceedings Vol. 9775:
Next-Generation Optical Networks for Data Centers and Short-Reach Links III
Atul K. Srivastava, Editor(s)

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