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Proceedings Paper

FPGA implementation of advanced FEC schemes for intelligent aggregation networks
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Paper Abstract

In state-of-the-art fiber-optics communication systems the fixed forward error correction (FEC) and constellation size are employed. While it is important to closely approach the Shannon limit by using turbo product codes (TPC) and low-density parity-check (LDPC) codes with soft-decision decoding (SDD) algorithm; rate-adaptive techniques, which enable increased information rates over short links and reliable transmission over long links, are likely to become more important with ever-increasing network traffic demands. In this invited paper, we describe a rate adaptive non-binary LDPC coding technique, and demonstrate its flexibility and good performance exhibiting no error floor at BER down to 10-15 in entire code rate range, by FPGA-based emulation, making it a viable solution in the next-generation high-speed intelligent aggregation networks.

Paper Details

Date Published: 13 February 2016
PDF: 7 pages
Proc. SPIE 9773, Optical Metro Networks and Short-Haul Systems VIII, 977309 (13 February 2016); doi: 10.1117/12.2214884
Show Author Affiliations
Ding Zou, The Univ. of Arizona (United States)
Ivan B. Djordjevic, The Univ. of Arizona (United States)


Published in SPIE Proceedings Vol. 9773:
Optical Metro Networks and Short-Haul Systems VIII
Atul K. Srivastava; Werner Weiershausen; Benjamin B. Dingel; Achyut K. Dutta, Editor(s)

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