Share Email Print
cover

Proceedings Paper

Yield improvement by wafer edge engineering
Author(s): Fred N. Hause; Daniel Kadoch; Dilip Wadhwani
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Improvements in defect reduction of semiconductor processes and equipment have realized higher wafer sorts yield but have typically limited analysis and inspection of the edge of wafers by several millimeters. Sort yield on production wafers has been observed to be reduced by glass flaking and other undesired structures created on wafer edges which defect inspection typically excludes and process equipment overlooks their effect. We have taken a systematic approach to characterize integrated wafer edge processing such as size and tolerance of clamping during film deposition and plasma etching. Characterization of wafer edge processing is further refined through the use of process simulations. This modeling allows for predictive effects of changes in edge schemes as well as effects of gradual process equipment deviations such as varying clamp size during target lifetime in PVD equipment. By characterizing and modeling wafer edge processing we are able to circumvent defects that are generated by processing conditions unlike what is called for by design rules.

Paper Details

Date Published: 22 September 1995
PDF: 8 pages
Proc. SPIE 2635, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, (22 September 1995); doi: 10.1117/12.221443
Show Author Affiliations
Fred N. Hause, Advanced Micro Devices, Inc. (United States)
Daniel Kadoch, Advanced Micro Devices, Inc. (United States)
Dilip Wadhwani, Univ. of Arizona (United States)


Published in SPIE Proceedings Vol. 2635:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis
Gopal Rao; Massimo Piccoli, Editor(s)

© SPIE. Terms of Use
Back to Top