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Proceedings Paper

ArMenX: a flexible platform for signal and image processing
Author(s): Guy Leonhard; Eric Cousin; Jean-Daniel Laisne; Jo Le Drezen; Gerald Ouvradou; Aymeric Poulain Maubant; Andre Thepaut
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Paper Abstract

The computation power needed in communication and image processing is increasing so much that parallel architecture can be seen as the only solution available. Serious drawbacks of such architectures are their lack of flexibility and the complexity of their programming. The goal of the ArMenX project is to offer a flexible development and prototyping platform for signal and image parallel processing. The ArMenX architecture consists of a set of replicated processing nodes. Each node consists of three tightly coupled units: a Transpute, a FPGA, and a DSP. The ArMenX nodes are interconnected by two media: one is an asynchronous serial link, and the other is a high bandwidth parallel ring. Thanks to this flexible multi-DSP architecture, ArMenX allows efficient implementation of a 'large kind of algorithms' involved in signal and image processing. We will present three examples of working applications on this parallel architecture: a parallel forward and backward propagation for neural network; a parallel implementation of computing an electromagnetic field (for an electrostatic and magnetostatic probelm) using an artificial neural network; and a large image compression algorithm using wavelet transform. The present work deals with the integration of a high level programming neural network environment. This environment will make it easier to take advantage of this architecture's flexibility.

Paper Details

Date Published: 19 September 1995
PDF: 12 pages
Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); doi: 10.1117/12.221347
Show Author Affiliations
Guy Leonhard, LIBr-Telecom Bretagne (France)
Eric Cousin, LIBr-Telecom Bretagne (France)
Jean-Daniel Laisne, LIBr-Telecom Bretagne (France)
Jo Le Drezen, LIBr-Telecom Bretagne (France)
Gerald Ouvradou, LIBr-Telecom Bretagne (France)
Aymeric Poulain Maubant, LIBr-Telecom Bretagne (France)
Andre Thepaut, LIBr-Telecom Bretagne (France)

Published in SPIE Proceedings Vol. 2607:
Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
John Schewel, Editor(s)

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