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Proceedings Paper

FPGA implementation of polynomial evaluation algorithms
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Paper Abstract

The most significant digit first function evaluation method (E-method) allows efficient evaluation of polynomials and certain rational fucntions on custon hardware. The time required for the computation is of the order of m carry-free addition operations, m being the number of digits in the result. We discuss a digit-parallel and a digit-serial implementation of this method on a DecPeRLe-1 board, made up with Xilinx FPGAs. After a presentation of the E-method, we give a discription of the architecture of the DecPeRLe-1 board, present our designs and analyze their performances.

Paper Details

Date Published: 19 September 1995
PDF: 12 pages
Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); doi: 10.1117/12.221338
Show Author Affiliations
Milos D. Ercegovac, Univ. of California/Los Angeles (United States)
Jean-Michel Muller, Ecole Normale Superieure de Lyon (France)
Arnaud Tisserand, Ecole Normale Superieure de Lyon (France)


Published in SPIE Proceedings Vol. 2607:
Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
John Schewel, Editor(s)

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