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Proceedings Paper

Low-cost hardware acceleration for volume visualization
Author(s): Michael Dao; Todd A. Cook; Deborah E. Silver
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Paper Abstract

Volume visualization is a popular method for viewing simulated or experimental 3D data sets from applications such as medical imaging, computational fluid dynamics, and climate modeling. However, most software and low-cost hardware implementations of visualization algorithms do not have sufficient performance for inter-active viewing. This paper discusses a method for low-cost, parallel hardware acceleration of volume rendering using a PC-hosted FPGA board. Our method uses a parallel distributed memory approach for compositing and tranformation of volume data, and it provides insight into efficient use of low-cost memory systems.

Paper Details

Date Published: 19 September 1995
PDF: 11 pages
Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); doi: 10.1117/12.221329
Show Author Affiliations
Michael Dao, Rutgers Univ. (United States)
Todd A. Cook, Rutgers Univ. (United States)
Deborah E. Silver, Rutgers Univ. (United States)


Published in SPIE Proceedings Vol. 2607:
Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
John Schewel, Editor(s)

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