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Proceedings Paper

Reconfigurable computing for multimedia DSP applications
Author(s): Erdogan Simsek; Abdul Wahab; Kishan Jainandunsing
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Paper Abstract

The application of reconfigurable computing to exploit the inherent serialism in DSP algorithms is investigated with the aim of building cost-effective, real-time hardware. The DSP algorithm is expected to be decomposed so that the most compute intensive and data flow oriented part is separated from the less compute intensive and more control flow oriented part. The different modules in the compute intensive part are expected to be serialized and implemented on a reconfigurable platform. The proposed architecture consists of an array of a minimum of two Field Programmable Gate Arrays (FPGAs). The FPGAa are grouped in two sets such that when one set executes the current batch of modules the second set could be configured to execute the next batch of modules. The control flow oriented part of the algorithm is implemented on a DSP processor.

Paper Details

Date Published: 19 September 1995
PDF: 8 pages
Proc. SPIE 2607, Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing, (19 September 1995); doi: 10.1117/12.221327
Show Author Affiliations
Erdogan Simsek, Nanyang Technological Univ. (Singapore)
Abdul Wahab, Nanyang Technological Univ. (Singapore)
Kishan Jainandunsing, Nanyang Technological Univ. (Singapore)

Published in SPIE Proceedings Vol. 2607:
Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing
John Schewel, Editor(s)

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