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Proceedings Paper

Relationships between process fundamentals, facility design, and production control of semiconductor manufacturing systems
Author(s): Shannon Chen; Rieko C. Hase; Kaine Mordaunt; Reha M. Uzsoy; Christos G. Takoudis
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Paper Abstract

Basic interrelationships among yields, processing environments, and shop-floor scheduling in semiconductor wafer fabrication facilities are currently under study. In this paper, we focus on a hypothetical wafer fabrication facility producing 3D CMOS devices designed and developed at Purdue. A key step of this sequence of this process is silicon selective epitaxial growth (SEG). Our emphasis is on the effects of substrate temperature, and system pressure on the quality of the films grown through silicon SEG. Such studies result in relationships between yield and processing conditions. For example, higher substrate temperatures, in the range of 800 to 1000 degree(s)C studied, appear to result in significantly lower defect densities for all sizes of seed windows investigated. Our experimental observations on relationships between yield and time can in turn can be used to examine the viability of different layouts for wafer fabrication facilities. We focus on cellular layouts, where machines are organized into cells, each dedicated to the processing of a certain subset of operations. For the 3D CMOS fab mentioned previously, we present results of simulation experiments that indicate that under certain conditions, cellular layouts result in better cycle time performance at the expense of some additional capital investment.

Paper Details

Date Published: 19 September 1995
PDF: 11 pages
Proc. SPIE 2637, Process, Equipment, and Materials Control in Integrated Circuit Manufacturing, (19 September 1995); doi: 10.1117/12.221317
Show Author Affiliations
Shannon Chen, Purdue Univ. (United States)
Rieko C. Hase, Purdue Univ. (United States)
Kaine Mordaunt, Purdue Univ. (United States)
Reha M. Uzsoy, Purdue Univ. (United States)
Christos G. Takoudis, Purdue Univ. (United States)

Published in SPIE Proceedings Vol. 2637:
Process, Equipment, and Materials Control in Integrated Circuit Manufacturing
Anant G. Sabnis; Ivo J. Raaijmakers, Editor(s)

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