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Proceedings Paper

Performance optimization of three-dimensional optoelectronic interconnection for intra-multi-chip-module clock signal distribution
Author(s): Chunhe Zhao; Ray T. Chen
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Paper Abstract

The structure, fabrication, and theory of a 3D planarized optoelectronic clock signal distribution device, based on a thin light-guiding substrate in conjunction with a 2D polymer holographic grating array, are described. We have previously demonstrated a 25 GHz 1-to-42 (6 X 7) highly parallel fanout interconnect with a signal to noise ration of 10 dB1. In this paper, theoretical work focused on generating a globally uniform fanout distribution is presented. An objective function aimed at equalizing the intensities among the fanout beams is established and optimization results are reported. Finally, the angular misalignment and wavelength dispersion problem are further discussed, together with their tolerance requirements on the size of the photoreceivers and the bandwidth of the vertical cavity surface emitting lasers integrated on the multi-chip-modules.

Paper Details

Date Published: 18 September 1995
PDF: 9 pages
Proc. SPIE 2638, Optical Characterization Techniques for High-Performance Microelectronic Device Manufacturing II, (18 September 1995); doi: 10.1117/12.221198
Show Author Affiliations
Chunhe Zhao, Univ. of Texas/Austin (United States)
Ray T. Chen, Univ. of Texas/Austin (United States)

Published in SPIE Proceedings Vol. 2638:
Optical Characterization Techniques for High-Performance Microelectronic Device Manufacturing II
John K. Lowell; Ray T. Chen; Jagdish P. Mathur, Editor(s)

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