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Proceedings Paper

Prediction of 0.18 um CMOS technology performance using tuned device simulation
Author(s): Mahalingam Nandakumar; Mark Rodder; Ih-Chin Chen
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Paper Abstract

For the design of a scaled CMOS technology, it becomes necessary to use predictive device simulation to improve MOSFET design and reduce the design cycle time. The results of a simulation study which is carried out to predict the performance of N and P channel MOSFETs with a physical gate length (Lg) of 0.18 micrometers are reported in this paper. The performance of the MOSFETs is estimated using a performance Figure of Merit (FOM[1]) calculated from their simulated I-V characteristics. This study is used to identify particular improvements to an existing 0.25 micrometers , 2.5 V, 60 A technology [2] so as to meet the FOM target at a 0.18 micrometers , 1.5 V, 36 A technology node.

Paper Details

Date Published: 15 September 1995
PDF: 8 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221153
Show Author Affiliations
Mahalingam Nandakumar, Texas Instruments Inc. (United States)
Mark Rodder, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)


Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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