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Proceedings Paper

15 ps cryogenic operation of 0.19-um-LG n+ - p+ double-gate SOI CMOS
Author(s): Toshihiro Sugii; Tetsu Tanaka; Hiroshi Horie; Kunihiro Suzuki
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Paper Abstract

We demonstrated a CMOS invertor with a 15 ps propagation delay (tpd) at 77 K. This device uses n+ - p+ double-gate SOI MOSFETs with a gate length (LG) of 0.19 micrometers and a gate oxide thickness (tox) around 9 nm. The channel doping concentration of this device is maintained as low as 1015 cm-3 even in the deep submicron gate length regime while maintaining short channel immunity. Therefore, the decreased phonon scattering due to the cryogenic operation causes a significant increase in mobility, which leads to smaller tpd than any other reported values for a given LG. Although the threshold voltage (Vth) increases with a decrease in temperature, we can adjust it for cryogenic operation by controlling tox and the SOI thicknesses (tSi).

Paper Details

Date Published: 15 September 1995
PDF: 9 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221150
Show Author Affiliations
Toshihiro Sugii, Fujitsu Labs. Ltd. (Japan)
Tetsu Tanaka, Fujitsu Labs. Ltd. (Japan)
Hiroshi Horie, Fujitsu Labs. Ltd. (Japan)
Kunihiro Suzuki, Fujitsu Labs. Ltd. (Japan)


Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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