Share Email Print
cover

Proceedings Paper

Dimension-temperature combination scaling for low-temperature 0.1micron CMOS
Author(s): Kazuya Masu; Michio Yokoyama; Kazuo Tsubouchi
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

High speed and high performance is essentially required in CMOS ULSI of super workstations in the 21st century's multimedia era with every possible means. Low temperature operation of CMOS ULSI should be re- recognized for high speed application, because the low-temperature operation can always exhibit 2-3 times higher operation speed than room- temperature operation when the same design-rule microfabrication process is utilized. In this paper, we discuss a temperature scaling theory (TST) and temperature-dimension combination scaling theory (CST) for 0.1 micrometers and below-0.1 micrometers MOSFET. Emphasis of the combination scaling is that the threshold voltage and the subthreshold swing are fully scaled for low-supply voltage operation. The fabricated 77K CST-MOSFET with 1-V supply voltage has the threshold voltage (Vth) of 0.21 V and the subthreshold swing (S) of 27 mV/dec without degradation of Vth and S due to the short-channel effects.

Paper Details

Date Published: 15 September 1995
PDF: 12 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221149
Show Author Affiliations
Kazuya Masu, Tohoku Univ. (Japan)
Michio Yokoyama, Tohoku Univ. (Japan)
Kazuo Tsubouchi, Tohoku Univ. (Japan)


Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

© SPIE. Terms of Use
Back to Top