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Proceedings Paper

Modeling limits of multilevel interconnect technology
Author(s): Bibiche Geuskens; Kenneth Rose
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Paper Abstract

Due to the continuing scaling down of minimum feature sizes, interconnect is becoming the limiting factor for on-chip performance. Alternative interconnect designs and new materials are needed to meet future performance expectations as predicted by the SIA Roadmap. We are developing models that can help designers in making initial evaluations about the possible performance impact of advanced interconnect designs and enhanced materials. In this paper, we apply these models to discuss the limitations of interconnect technology. In particular, we focus on the effects of interconnect materials on chip performance issues.

Paper Details

Date Published: 15 September 1995
PDF: 9 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221146
Show Author Affiliations
Bibiche Geuskens, Rensselaer Polytechnic Institute (United States)
Kenneth Rose, Rensselaer Polytechnic Institute (United States)


Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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