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Proceedings Paper

Characterization of SOG (spin on glass) fully etch back process for multilevel interconnection technology
Author(s): Y. C. Huang; Marx Huang; Sen-Fu Chen; C. H. Yu; L. M. Liu; M. S. Lin
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Paper Abstract

This investigation characterized SOG (spin on glass) fully etch back process for submicron multilevel interconnection planarization with the CHF3/CF4 etching chemistry in a conventional RIE (reactive ion etching) oxide etcher. The correlations of SOG fully etch back results with the tool controlled parameters such as pressure, magnetic field strength, bottom electrode temperature, CHF3/CF4 gas flow ratio, and backside helium pressure are completely studied. The selectivity of the PEOX (plasma-enhanced CVD oxide) to SOG and the uniformity of etching are investigated to ensure good planarization performance. It is found that high selectivity of PEOX to SOG process can effectively reduce the microloading effects and improve the planarization during SOG etch back. However, too high selectivity may result in bumped or rough SOG surface. Uniformity is basically affected by the SOG etch rate uniformity, the as-coated SOG thickness variation, and the selectivity. Several approaches are examined to achieve the best uniformity. Finally, with the combination of high selectivity of PEOX to SOG and the uniform etching, good planarization can be achieved in the SOG fully etch back process.

Paper Details

Date Published: 15 September 1995
PDF: 10 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221143
Show Author Affiliations
Y. C. Huang, Taiwan Semiconductor Manufacturing Co. (Taiwan)
Marx Huang, Taiwan Semiconductor Manufacturing Co. (Taiwan)
Sen-Fu Chen, Taiwan Semiconductor Manufacturing Co. (Taiwan)
C. H. Yu, Taiwan Semiconductor Manufacturing Co. (Taiwan)
L. M. Liu, Taiwan Semiconductor Manufacturing Co. (Taiwan)
M. S. Lin, Taiwan Semiconductor Manufacturing Co. (Taiwan)


Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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