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Proceedings Paper

Latch-up temperature dependence of majority carrier guard structures up to 250-degrees C
Author(s): Dirk Uffmann; Jens Stemmer; Hans-Ulrich Schroeder; Joerg Ackermann; Jochen Aderhold
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Paper Abstract

The purpose of this work was to investigate the latch-up temperature dependence of majority carrier guard structures with the goal to find design rules for latch-up free high temperature operation of a CMOS- ASIC. Measurements up to 250 degree(s)C show an enhanced latch-up resistance of majority carrier guards compared to conventional electrode placement. With increasing temperature holding voltage and current decrease for both types. The test devices have also been simulated using 2D FEM device simulation. For majority carrier guard structures it is essential to use Fermi-Dirac-statistics instead of Boltzmann-statistics and a mobility model which accounts for carrier-carrier scattering in order to get accurate simulation results. In a further step the simulations were used to predict the necessary guard width for holding voltages higher than 5V to gain absolutely latch-up free operation at 250 degree(s)C. The results can be exploited for the design of temperature resistant, latch- up free CMOS circuits. The work is relevant for an ongoing effort to make use of junction isolated CMOS technology for temperature resistant electronics up to 250 degree(s)C.

Paper Details

Date Published: 15 September 1995
PDF: 12 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221140
Show Author Affiliations
Dirk Uffmann, Univ. Hannover (Germany)
Jens Stemmer, Univ. Hannover (Germany)
Hans-Ulrich Schroeder, Univ. Hannover (Germany)
Joerg Ackermann, Univ. Hannover (Germany)
Jochen Aderhold, Univ. Hannover (Germany)


Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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