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Proceedings Paper

Ultra-low loss fully-etched grating couplers for perfectly vertical coupling compatible with DUV lithography tools
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Paper Abstract

Hybrid integration of VCSELs onto silicon-on-insulator (SOI) substrates has emerged as an attractive approach for bridging the gap between cost-effective and energy-efficient directly modulated laser sources and silicon-based PICs by leveraging flip-chip (FC) bonding techniques and silicon grating couplers (GCs). In this context, silicon GCs, should comply with the process requirements imposed by the complimentary-metal-oxide-semiconductor manufacturing tools addressing in parallel the challenges originating from the perfectly vertical incidence. Firstly, fully etched GCs compatible with deep-ultraviolet lithography tools offering high coupling efficiencies are imperatively needed to maintain low fabrication cost. Secondly, GC's tolerance to VCSEL bonding misalignment errors is a prerequisite for practical deployment. Finally, a major challenge originating from the perfectly vertical coupling scheme is the minimization of the direct back-reflection to the VCSEL’s outgoing facet which may destabilize its operation. Motivated from the above challenges, we used numerical simulation tools to design an ultra-low loss, bidirectional VCSEL-to-SOI optical coupling scheme for either TE or TM polarization, based on low-cost fully etched GCs with a Si-layer of 340 nm without employing bottom reflectors or optimizing the buried-oxide layer. Comprehensive 2D Finite-Difference-Time- Domain simulations have been performed. The reported GC layout remains fully compatible with the back-end-of-line (BEOL) stack associated with the 3D integration technology exploiting all the inter-metal-dielectric (IMD) layers of the CMOS fab. Simulation results predicted for the first time in fully etched structures a coupling efficiency of as low as -0.87 dB at 1548 nm and -1.47 dB at 1560 nm with a minimum direct back-reflection of -27.4 dB and -14.2 dB for TE and TM polarization, respectively.

Paper Details

Date Published: 14 March 2016
PDF: 7 pages
Proc. SPIE 9752, Silicon Photonics XI, 975212 (14 March 2016); doi: 10.1117/12.2211374
Show Author Affiliations
G. Dabos, Aristotle Univ. of Thessaloniki (Greece)
N. Pleros, Aristotle Univ. of Thessaloniki (Greece)
Informatics and Telematics Institute (Greece)
D. Tsiokos, Aristotle Univ. of Thessaloniki (Greece)
Informatics and Telematics Institute (Greece)


Published in SPIE Proceedings Vol. 9752:
Silicon Photonics XI
Graham T. Reed; Andrew P. Knights, Editor(s)

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