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Proceedings Paper

CMOS LDD process with seven masking steps from well to passivation
Author(s): Jeong Yeol Choi; Chung Jen Chien; Chung Chyung Han; Chuen-Der Lien
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Paper Abstract

A cost-effective CMOS LDD process is described. This process, if single polysilicon and single metal, uses total of only seven masking steps: well, isolation, gate, source/drain, contact, metal, and passivation. Main strategy of the process is to implant blanket for one type of doping regions and compensated with masked implants for the other type. In our embodiment, blanket n-well is formed by implant and high- temperature drive-in before LOCOS isolation. Masked retrograde p-well is formed with multiple implants after LOCOS in order to fulfill different doping requirements for channel and field regions at one masking step. After gate definition, blanket n-LDD implant is performed, followed by side-wall spacer formation and blanket n+ source/drain implant. With p+ mask, three processing steps are performed: p+ source/drain implant, spacer removal and p-LDD implant. Finally, contact formation, metalization and passivation complete the process. The device parameters such as minimum gate length, VT, isolation, etc. are kept unchanged, compared to those of original non-compensated doping process. Some resistances and capacitances increase 20%.

Paper Details

Date Published: 15 September 1995
PDF: 5 pages
Proc. SPIE 2636, Microelectronic Device and Multilevel Interconnection Technology, (15 September 1995); doi: 10.1117/12.221122
Show Author Affiliations
Jeong Yeol Choi, Integrated Device Technology (United States)
Chung Jen Chien, Integrated Device Technology (United States)
Chung Chyung Han, Integrated Device Technology (United States)
Chuen-Der Lien, Integrated Device Technology (United States)

Published in SPIE Proceedings Vol. 2636:
Microelectronic Device and Multilevel Interconnection Technology
Ih-Chin Chen; Girish A. Dixit; Trung Tri Doan; Nobuo Sasaki, Editor(s)

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