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Proceedings Paper

Novel fast multiplier implemented using FPGA
Author(s): Janusz Jabłoński; Marek Węgrzyn
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Paper Abstract

In the paper, the solution dedicated for FPGA devices of a synthesis of parallel multiplication systems with the alternative approach, called mutual exclusion, for results of partial products is presented. There are proposed a reducer with the factor 4:2 for parallel multipliers, based on Wallace tree structures, that are dedicated for 4-input and 1-output Look-Up Table (LUT) function generator used in FPGA devices. The elaboration refers to the solution for multiplying using FPGAs the numbers of 4 and 8 bits. However it can be enlarged up to 16 and 32 bits. The proposed solution gives the opportunity to use the probability of conditional significant partial products and faster service - fewer logic levels for special cases of multiplication related to the specific values of the sums of partial product bits.

Paper Details

Date Published: 11 September 2015
PDF: 10 pages
Proc. SPIE 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 96623Z (11 September 2015); doi: 10.1117/12.2206018
Show Author Affiliations
Janusz Jabłoński, Univ. of Zielona Gora (Poland)
Marek Węgrzyn, Univ. of Zielona Gora (Poland)


Published in SPIE Proceedings Vol. 9662:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015
Ryszard S. Romaniuk, Editor(s)

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