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Proceedings Paper

ASIC-based architecture for the real-time computation of 2D convolution with large kernel size
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Paper Abstract

Bidimensional convolution is a low-level processing algorithm of interest in many areas, but its high computational cost constrains the size of the kernels, especially in real-time embedded systems. This paper presents a hardware architecture for the ASIC-based implementation of 2-D convolution with medium–large kernels. Aiming to improve the efficiency of storage resources on-chip, reducing off-chip bandwidth of these two issues, proposed construction of a data cache reuse. Multi-block SPRAM to cross cached images and the on-chip ping-pong operation takes full advantage of the data convolution calculation reuse, design a new ASIC data scheduling scheme and overall architecture. Experimental results show that the structure can achieve 40× 32 size of template real-time convolution operations, and improve the utilization of on-chip memory bandwidth and on-chip memory resources, the experimental results show that the structure satisfies the conditions to maximize data throughput output , reducing the need for off-chip memory bandwidth.

Paper Details

Date Published: 14 December 2015
PDF: 6 pages
Proc. SPIE 9814, MIPPR 2015: Parallel Processing of Images and Optimization; and Medical Imaging Processing, 981405 (14 December 2015); doi: 10.1117/12.2205642
Show Author Affiliations
Rui Shao, Huazhong Univ. of Science and Technology (China)
Sheng Zhong, Huazhong Univ. of Science and Technology (China)
Luxin Yan, Huazhong Univ. of Science and Technology (China)


Published in SPIE Proceedings Vol. 9814:
MIPPR 2015: Parallel Processing of Images and Optimization; and Medical Imaging Processing
Jianguo Liu, Editor(s)

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