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Proceedings Paper

Algorithmic synthesis using Python compiler
Author(s): Radoslaw Cieszewski; Ryszard Romaniuk; Krzysztof Pozniak; Maciej Linczuk
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Paper Abstract

This paper presents a python to VHDL compiler. The compiler interprets an algorithmic description of a desired behavior written in Python and translate it to VHDL. FPGA combines many benefits of both software and ASIC implementations. Like software, the programmed circuit is flexible, and can be reconfigured over the lifetime of the system. FPGAs have the potential to achieve far greater performance than software as a result of bypassing the fetch-decode-execute operations of traditional processors, and possibly exploiting a greater level of parallelism. This can be achieved by using many computational resources at the same time. Creating parallel programs implemented in FPGAs in pure HDL is difficult and time consuming. Using higher level of abstraction and High-Level Synthesis compiler implementation time can be reduced. The compiler has been implemented using the Python language. This article describes design, implementation and results of created tools.

Paper Details

Date Published: 11 September 2015
PDF: 8 pages
Proc. SPIE 9662, Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015, 96623J (11 September 2015); doi: 10.1117/12.2205609
Show Author Affiliations
Radoslaw Cieszewski, Warsaw Univ. of Technology (Poland)
Ryszard Romaniuk, Warsaw Univ. of Technology (Poland)
Krzysztof Pozniak, Warsaw Univ. of Technology (Poland)
Maciej Linczuk, Warsaw Univ. of Technology (Poland)


Published in SPIE Proceedings Vol. 9662:
Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments 2015
Ryszard S. Romaniuk, Editor(s)

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