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Proceedings Paper

Implementation of weighted summation type fractional Fourier transform on FPGA
Author(s): Qiming Zou; Longlong Li; Qian Huang; Fei Wang
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Paper Abstract

Recently Fractional Fourier transform (FrFT) has got a variety of applications in digital signal and image processing. This paper presents a novel hardware architecture for real-time computation of Discrete Fractional Fourier Transform (DFrFT), which can easily be extended to other fractional transforms. The proposed architecture has been verified on Xilinx FPGA(XC6VLX240T), which can run at a frequency up to 291MHz while with high accuracy.

Paper Details

Date Published: 6 July 2015
PDF: 8 pages
Proc. SPIE 9631, Seventh International Conference on Digital Image Processing (ICDIP 2015), 963125 (6 July 2015); doi: 10.1117/12.2197111
Show Author Affiliations
Qiming Zou, Harbin Institute of Technology (China)
Longlong Li, Harbin Institute of Technology (China)
Qian Huang, Wright State Univ. (United States)
Fei Wang, Harbin Institute of Technology (China)


Published in SPIE Proceedings Vol. 9631:
Seventh International Conference on Digital Image Processing (ICDIP 2015)
Charles M. Falco; Xudong Jiang, Editor(s)

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