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Proceedings Paper

Enabling the 14nm node contact patterning using advanced RET solutions
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Paper Abstract

The 14nm node designs is getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. One of the most critical processes is the contact patterning due to the very aggressive design rules and the process window which becomes quickly limited. Despite the large number of RET applied, some hotspot configurations remain challenging. It becomes increasingly challenging to achieve sufficient process windows around the hot spots just using conventional process such as OPC and rule-based SRAF insertion. Although, it might be desirable to apply Inverse Lithography Technique (ILT) on all hot spots to guarantee ideal mask quality. However, because of the high number of hot spots to repair in the design, that solution might be much time consuming in term of OPC and mask processing.

In this paper we present a hybrid OPC solution based on local ILT usage around hot spots. It is named as Local Printability Enhancement (LPE) flow. First, conventional OPC and SRAF placement is applied on the whole design. Then, we apply LPE solution only on the remaining problematic hot spots of the design. The LPE flow also takes into account the mask rules so that it maintains the mask rule check (MRC) compliance through the borders of the repaired hot spot’s areas. We will demonstrate that the LPE flow enlarges the process window around hot spots and gives better lithography quality than baseline. The simulation results are confirmed on silicon wafer where all the hot spots are printed. We will demonstrate that LPE flow enlarges the depth of focus of the most challenging hot spot by 30nm compared to POR conventional solution. Because the proposed flow applies ILT solution on very local hot spot areas, the total OPC run time remains acceptable from manufacturing side.

Paper Details

Date Published: 4 September 2015
PDF: 9 pages
Proc. SPIE 9661, 31st European Mask and Lithography Conference, 96610Q (4 September 2015); doi: 10.1117/12.2193772
Show Author Affiliations
N. Zeggaoui, Mentor Graphics Corp. (France)
G. Landie, STMicroelectronics (France)
A. Villaret, STMicroelectronics (France)
V. Farys, STMicroelectronics (France)
E. Yesilada, STMicroelectronics (France)
A. Tritchkov, Mentor Graphics Corp. (United States)
J. Word, Mentor Graphics Corp. (United States)


Published in SPIE Proceedings Vol. 9661:
31st European Mask and Lithography Conference
Uwe F.W. Behringer; Jo Finders, Editor(s)

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