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Proceedings Paper

SOI layout decomposition for double patterning lithography on high-performance computer platforms
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Paper Abstract

In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on 45 nm Nangate Open Cell Library including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.

Paper Details

Date Published: 18 December 2014
PDF: 6 pages
Proc. SPIE 9440, International Conference on Micro- and Nano-Electronics 2014, 94400X (18 December 2014); doi: 10.1117/12.2180809
Show Author Affiliations
Vladimir Verstov, Bauman Moscow State Technical Univ. (Russian Federation)
Lyudmila Zinchenko, Bauman Moscow State Technical Univ. (Russian Federation)
Vladimir Makarchuk, Bauman Moscow State Technical Univ. (Russian Federation)


Published in SPIE Proceedings Vol. 9440:
International Conference on Micro- and Nano-Electronics 2014
Alexander A. Orlikovsky, Editor(s)

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