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Proceedings Paper

Implementation and performance of FPGA-accelerated particle flow filter
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Paper Abstract

The particle flow filters, proposed by Daum & Hwang, provide a powerful means for density-based nonlinear filtering but their computation is intense and may be prohibitive for real-time applications. This paper proposes a design for superfast implementation of the exact particle flow filter using a field-programmable gate array (FPGA) as a parallel environment to speedup computation. Simulation results from a nonlinear filtering example are presented to demonstrate that using FPGA can dramatically accelerate particle flow filters through parallelization at the expense of a tolerable loss in accuracy as compared to nonparallel implementation.

Paper Details

Date Published: 2 September 2015
PDF: 12 pages
Proc. SPIE 9596, Signal and Data Processing of Small Targets 2015, 95960B (2 September 2015); doi: 10.1117/12.2179546
Show Author Affiliations
Dimitrios Charalampidis, Univ. of New Orleans (United States)
Vesselin P. Jilkov, Univ. of New Orleans (United States)
Jiande Wu, Univ. of New Orleans (United States)

Published in SPIE Proceedings Vol. 9596:
Signal and Data Processing of Small Targets 2015
Oliver E. Drummond; Richard D. Teichgraeber, Editor(s)

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