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Proceedings Paper

VLSI chip architecture design for 2-D gray-level morphological operations
Author(s): Kun-Min Yang; Petros Maragos; Lance T. Wu
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Paper Abstract

The basic operations of mathematical morphology are quite useful for a broad area of image processing and analysis tasks. All morphological operations can be built from erosions and dilations. In this paper we develop a single chip VLSI architecture of an erosion/dilation algorithm for real-time image processing. The new architecture allows sequential inputs and performs parallel processing with 100 percent efficiency. The erosions (mm of differences) and dilations (max of additions) operate on 2-D gray-level image signals and use a 5 x 5-pixel gray-level structuring element. Two chips can be cascaded for a 7 x 7 structuring element. The overall chip design also provides the user with sufficient flexibility to optionally offset the output images by adding a constant level and/or scale their dynamic range. 1.

Paper Details

Date Published: 1 September 1990
PDF: 10 pages
Proc. SPIE 1297, Hybrid Image and Signal Processing II, (1 September 1990); doi: 10.1117/12.21330
Show Author Affiliations
Kun-Min Yang, Bell Communications Research (United States)
Petros Maragos, Harvard Univ. (United States)
Lance T. Wu, Bell Communications Research (United States)

Published in SPIE Proceedings Vol. 1297:
Hybrid Image and Signal Processing II
David P. Casasent; Andrew G. Tescher, Editor(s)

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