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Proceedings Paper

Reduction of ASIC gate-level line-end shortening by mask compensation
Author(s): Joseph G. Garofalo; John DeMarco; J. Bailey; Jiabei Xiao; Sheila Vaidya
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Paper Abstract

One of the most dramatic effects that one encounters when attempting the optical imaging of 0.5 k ASIC gate levels is the truncation or shortening of transistor geometries. This reduces the wafer process latitude and in some cases even eliminates the level-to-level overlay margin. We investigate a number of techniques, including various complexities of mask compensation and modified illumination to mitigate this phenomenon in manners sufficiently general to accommodate ASIC layouts.

Paper Details

Date Published: 26 May 1995
PDF: 13 pages
Proc. SPIE 2440, Optical/Laser Microlithography VIII, (26 May 1995); doi: 10.1117/12.209250
Show Author Affiliations
Joseph G. Garofalo, AT&T Bell Labs. (United States)
John DeMarco, AT&T Bell Labs. (United States)
J. Bailey, AT&T Bell Labs. (United States)
Jiabei Xiao, AT&T Bell Labs. (United States)
Sheila Vaidya, AT&T Bell Labs. (United States)

Published in SPIE Proceedings Vol. 2440:
Optical/Laser Microlithography VIII
Timothy A. Brunner, Editor(s)

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